Because of advanced system requirements such as increased communications, algorithm complexity, safety critical requirements and such like, microcontroller technology requirements will be impacted.
CPU trends
An effect of the increased throughput requirements driven by algorithm complexity is the requirement for very high performance, low cost CPUs. As well as providing a very high throughput and fast interrupt handling capabilities, the CPU must also be conducive to generating efficient dense code when a C compiler is used. As the CPU is now usually a relatively small area of the die with respect to memory arrays, if a CPU is designed in a high-level language friendly way, a significant amount of memory (and hence cost) can be saved.
There is also a trend to use high-performance RISC CPUs in automotive microcontrollers in preference to the traditional CISC units. This trend will continue. Traditionally, what has set RISC apart from CISC is the ability to execute an instruction in a single clock cycle and the fact that RISC machines do not use microcode to decode instructions, but are hardwired.
It has been argued that the vast majority of most software consists of very simple instructions. The philosophy of RISC is to produce processors that can execute these simple instructions (such as ADD, SUB, SHIFT, etc.) in one clock cycle. More complex instructions such as MUL and DIV were not available on early RISC processors.
When an opcode is generated by a line of software in a CISC machine, this opcode is basically an address for a microcode memory (also sometimes called a 'control store') which points to a certain string of control bits that are applied to the execution unit (via a small amount of combinational control logic). These bits include many control signals to ensure that the execution unit performs the desired function. This microcode memory is a regularly structured array, which is straightforward to design and offers flexibility to the designer, allowing him to design the optimum microcode.
A RISC processor does not have a microcode memory. Therefore the opcode, which is generated in software, is applied directly to a larger array of combinational control logic in order to generate all the appropriate signals to operate the execution unit. This is a more complex design, which results in a smaller silicon size (as there is no microcode memory) and usually faster operating speed.
The distinction of single clock instructions for RISC only is becoming more vague as many RISC CPUs now include complex instructions which can take several cycles to execute. RISC processors only allow operations to be performed directly between registers in the CPU. This means that if we had two bytes in memory that we wanted to AND together, we would have to first load them into CPU registers. CISC machines would normally allow you to AND a user register with a location outside the programmers model.
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