Multiplication in FPGA Design!!

 

 Multiplication is basically a shift add operation.  There are, however, many variations on how to do it.  Some are more suitable for FPGA use than others.   This page is a brief tutorial on multiplication hardware.  The hyperlinked items in this list are currently in the text.  The remaining items will be added in a future release of this page.

Scaling Accumulator Multipliers

	Parallel by serial algorithm
	Iterative shift add routine
	N clock cycles to complete
	Very compact design
	Serial input can be MSB or LSB first depending on direction of shift in accumulator
	Parallel output

A scaling accumulator multiplier performs multiplication using an iterative shift-add routine.  One input is presented in bit parallel form while the other is in bit serial form.  Each bit in the serial input multiplies the parallel input by either 0 or 1.  The parallel input is held constant while each bit of the serial input is presented.  Note that the one bit multiplication either passes the parallel input unchanged or substitutes zero.  The result from each bit is added to an accumulated sum.  That sum is shifted one bit before the result of the next bit multiplication is added to it.